1. Field of the Invention
The present invention relates to a method for forming short-channel transistors, and more particularly to a method for forming transistors having short-channels using a damascene process.
2. Description of the Prior Art
As generally known in the art, in a transistor, since the length of a gate of N-channel Metal Oxide Semiconductor (NMOS) has become to be reduced below 0.14 μm, a short channel effect (SCE) could not be gradually restricted. In order to restrict SCE, effective length of the channel should be basically increased. To this end, a reduction of dose rate in a lightly doped drain (LDD) region is effective.
However, the reduction of dose rate in an LDD region causes a degradation of a device by hot carrier effects because of a reduction of an effect of electric field relief, and causes a reduction of through-current because of an increase of resistance of LDD region, which makes it difficult to obtain high performance products.
Meanwhile, in order to form an LDD region, an implantation of P or As ions can be conducted whereby a degradation of a device by hot carrier effects may be effectively prevented, but the horizontal and vertical extensions of an LDD by an implantation of P ions are large to a great extent because a diffusion by an annealing treatment is larger than that by As ion implantation.
Generally, dose rate of ion implants to sufficiently secure device performance (i.e., capable of reducing resistance of an LDD region) is above 3×1013/cm2, which dose rate corresponds to high dose rate in a 0.14 μm-class technology, causing a problem in that an SCE cannot be restricted.
Also, where As ions are adapted as implant impurities of an LDD region, diffusion by an annealing treatment is very smaller than that by P ion implantation, which effectively restricts an SCE. Nevertheless resistance of an LDD region can be reduced sufficient to secure through-current of a device, there is provided a problem in that hot carrier feature is worse than that in P implanted LDD region.